Model-based PPC verification methodology with two dimensional pattern feature extraction

Proc. SPIE, Vol. 5040, 1156 (2003); doi:10.1117/12.485511

Online Publication Date: 3 February 2004

Conference Date: Tuesday 25 February 2003
Conference Location: Santa Clara, CA, USA
Conference Title: Optical Microlithography XVI
Conference Chairs: Anthony Yen

ABSTRACT

CITING ARTICLES

 
Toshiba Corp. (Japan)

A Novel model-based process proximity correction (PPC) verification methodology is proposed. This methodology features the comparison between actual processed wafers and target CAD data. The new system makes it possible to compare extracted two-dimensional pattern features on actual processed wafers with target pattern features on CAD data at any "hot spot" patterns. The "hot spot" patterns have relatively large CD errors on wafers after PPC in lithography simulation. In addition to this methodology, the model-based PPC verification flow was constructed with a feedback loop of the results. The application of this methodology to the 90nm-node CMOS gate yielded useful information on accurate CD control. The qualitative and quantitative consideration from the results indicated suitable subsequent actions regarding wafer fabrication, mask re-fabrication, PPC re-modeling and PPC re-parameterization in the feedback loop.

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